使用verilog HDL 16位cpu设计

[{"title":"（ 19 个子文件 430KB ） 使用verilog HDL 16位cpu设计","children":[{"title":"16位cpu设计","children":[{"title":"test5.dat <span style='color:#111;'> 2.59KB </span>","children":null,"spread":false},{"title":"test1.pro <span style='color:#111;'> 3.25KB </span>","children":null,"spread":false},{"title":"rom.v <span style='color:#111;'> 235B </span>","children":null,"spread":false},{"title":"ram.v <span style='color:#111;'> 378B </span>","children":null,"spread":false},{"title":"vsim.wlf <span style='color:#111;'> 256.00KB </span>","children":null,"spread":false},{"title":"test.v <span style='color:#111;'> 7.89KB </span>","children":null,"spread":false},{"title":"test4.pro <span style='color:#111;'> 3.29KB </span>","children":null,"spread":false},{"title":"test2.dat <span style='color:#111;'> 840B </span>","children":null,"spread":false},{"title":"test4.dat <span style='color:#111;'> 1.03KB </span>","children":null,"spread":false},{"title":"test5.PRO <span style='color:#111;'> 8.04KB </span>","children":null,"spread":false},{"title":"decoder.v <span style='color:#111;'> 537B </span>","children":null,"spread":false},{"title":"test2.pro <span style='color:#111;'> 1.90KB </span>","children":null,"spread":false},{"title":"test1.dat <span style='color:#111;'> 811B </span>","children":null,"spread":false},{"title":"RISC_CPU设计练习.doc <span style='color:#111;'> 810.00KB </span>","children":null,"spread":false},{"title":"CPU.v <span style='color:#111;'> 5.15KB </span>","children":null,"spread":false},{"title":"test3.dat <span style='color:#111;'> 886B </span>","children":null,"spread":false},{"title":"说明.txt <span style='color:#111;'> 906B </span>","children":null,"spread":false},{"title":"test3.pro <span style='color:#111;'> 1.56KB </span>","children":null,"spread":false},{"title":"模拟结果.txt <span style='color:#111;'> 10.56KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]