单周期CPUverilog实现

[{"title":"（ 14 个子文件 10KB ） 单周期CPUverilog实现","children":[{"title":"new","children":[{"title":"led.v <span style='color:#111;'> 780B </span>","children":null,"spread":false},{"title":"RAM.v <span style='color:#111;'> 1.42KB </span>","children":null,"spread":false},{"title":"ROM.v <span style='color:#111;'> 517B </span>","children":null,"spread":false},{"title":"DispalyDigit.v <span style='color:#111;'> 3.37KB </span>","children":null,"spread":false},{"title":"PC.v <span style='color:#111;'> 710B </span>","children":null,"spread":false},{"title":"Select.v <span style='color:#111;'> 941B </span>","children":null,"spread":false},{"title":"decode.v <span style='color:#111;'> 819B </span>","children":null,"spread":false},{"title":"ALU.v <span style='color:#111;'> 4.67KB </span>","children":null,"spread":false},{"title":"Extend.v <span style='color:#111;'> 959B </span>","children":null,"spread":false},{"title":"RegFile.v <span style='color:#111;'> 1.04KB </span>","children":null,"spread":false},{"title":"NPC.v <span style='color:#111;'> 775B </span>","children":null,"spread":false},{"title":"Display.v <span style='color:#111;'> 1.25KB </span>","children":null,"spread":false},{"title":"control.v <span style='color:#111;'> 5.43KB </span>","children":null,"spread":false},{"title":"Tongji.v <span style='color:#111;'> 1.49KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]