Xilinx Basy2板子动态显示译码加计数器Verilog HDL程序

[{"title":"（ 120 个子文件 3.72MB ） Xilinx Basy2板子动态显示译码加计数器Verilog HDL程序","children":[{"title":"num.bin <span style='color:#111;'> 2.64KB </span>","children":null,"spread":false},{"title":"hdllib.ref <span style='color:#111;'> 104B </span>","children":null,"spread":false},{"title":"jishuqi.bin <span style='color:#111;'> 8.02KB </span>","children":null,"spread":false},{"title":"isim.log <span style='color:#111;'> 648B </span>","children":null,"spread":false},{"title":"jishuqi.projectmgr <span style='color:#111;'> 7.94KB </span>","children":null,"spread":false},{"title":"......","children":null,"spread":false},{"title":"<span style='color:steelblue;'>文件过多，未全部展示</span>","children":null,"spread":false}],"spread":true}]