基于verilog的信号发生器

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</span>","children":null,"spread":false},{"title":"__ISE_repository_123.ise_.lock <span style='color:#111;'> 144B </span>","children":null,"spread":false},{"title":"DDS.ncd <span style='color:#111;'> 11.78KB </span>","children":null,"spread":false},{"title":"DDS_guide.ncd <span style='color:#111;'> 11.78KB </span>","children":null,"spread":false},{"title":"DDS.lso <span style='color:#111;'> 6B </span>","children":null,"spread":false},{"title":"DDS.prj <span style='color:#111;'> 22B </span>","children":null,"spread":false},{"title":"DDS.ngc <span style='color:#111;'> 8.70KB </span>","children":null,"spread":false},{"title":"DDS.xst <span style='color:#111;'> 71B </span>","children":null,"spread":false},{"title":"DDS_map.ncd <span style='color:#111;'> 6.88KB </span>","children":null,"spread":false},{"title":"dds.twx <span style='color:#111;'> 17.14KB </span>","children":null,"spread":false},{"title":"DDS_pad.csv <span style='color:#111;'> 8.79KB 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