[{"title":"( 42 个子文件 30KB ) 一个简单双核CPU的verilog实现(加中断、异常处理,已通过实验箱验证)","children":[{"title":"verilog codes","children":[{"title":"mux21.v <span style='color:#111;'> 754B </span>","children":null,"spread":false},{"title":"clock.v <span style='color:#111;'> 632B </span>","children":null,"spread":false},{"title":"t_clock.v <span style='color:#111;'> 850B </span>","children":null,"spread":false},{"title":"ALU.v <span style='color:#111;'> 1.48KB </span>","children":null,"spread":false},{"title":"div.v <span style='color:#111;'> 2.44KB </span>","children":null,"spread":false},{"title":"t_PC.v <span style='color:#111;'> 1.29KB </span>","children":null,"spread":false},{"title":"time_counter.v <span style='color:#111;'> 887B </span>","children":null,"spread":false},{"title":"SP.v <span style='color:#111;'> 1.29KB </span>","children":null,"spread":false},{"title":"mul1.v <span style='color:#111;'> 874B </span>","children":null,"spread":false},{"title":"mux41.v <span style='color:#111;'> 923B </span>","children":null,"spread":false},{"title":"KD_CPU.v <span style='color:#111;'> 6.48KB </span>","children":null,"spread":false},{"title":"t_memory.v <span style='color:#111;'> 1.19KB </span>","children":null,"spread":false},{"title":"memory.v <span style='color:#111;'> 902B </span>","children":null,"spread":false},{"title":"mux4.v <span style='color:#111;'> 1.81KB </span>","children":null,"spread":false},{"title":"shield.v <span style='color:#111;'> 527B </span>","children":null,"spread":false},{"title":"general_CU.v <span style='color:#111;'> 1.31KB </span>","children":null,"spread":false},{"title":"newIR.v <span style='color:#111;'> 991B </span>","children":null,"spread":false},{"title":"CX.v <span style='color:#111;'> 976B </span>","children":null,"spread":false},{"title":"mux2.v <span style='color:#111;'> 803B </span>","children":null,"spread":false},{"title":"t_div.v <span style='color:#111;'> 1.35KB </span>","children":null,"spread":false},{"title":"div_test.v <span style='color:#111;'> 1.15KB </span>","children":null,"spread":false},{"title":"sheild.v <span style='color:#111;'> 857B </span>","children":null,"spread":false},{"title":"testbench.v <span style='color:#111;'> 7.84KB </span>","children":null,"spread":false},{"title":"data_out.v <span style='color:#111;'> 662B </span>","children":null,"spread":false},{"title":"t_mux4.v <span style='color:#111;'> 1.24KB </span>","children":null,"spread":false},{"title":"t_mux41.v <span style='color:#111;'> 1.22KB </span>","children":null,"spread":false},{"title":"PC.v <span style='color:#111;'> 930B </span>","children":null,"spread":false},{"title":"register.v <span style='color:#111;'> 991B </span>","children":null,"spread":false},{"title":"interrupt_register.v <span style='color:#111;'> 814B </span>","children":null,"spread":false},{"title":"time_test.v <span style='color:#111;'> 1.03KB </span>","children":null,"spread":false},{"title":"t_ALU.v <span style='color:#111;'> 1.53KB </span>","children":null,"spread":false},{"title":"GR.v <span style='color:#111;'> 2.31KB </span>","children":null,"spread":false},{"title":"general_CPU.v <span style='color:#111;'> 2.00KB </span>","children":null,"spread":false},{"title":"interrupt.v <span style='color:#111;'> 772B </span>","children":null,"spread":false},{"title":"CPU1.v <span style='color:#111;'> 6.58KB </span>","children":null,"spread":false},{"title":"CU.v <span style='color:#111;'> 10.15KB </span>","children":null,"spread":false},{"title":"PC1.v <span style='color:#111;'> 944B </span>","children":null,"spread":false},{"title":"int_chart.v <span style='color:#111;'> 977B </span>","children":null,"spread":false},{"title":"t_mux2.v <span style='color:#111;'> 1.06KB </span>","children":null,"spread":false},{"title":"t_register.v <span style='color:#111;'> 1.24KB </span>","children":null,"spread":false},{"title":"CU1.v <span style='color:#111;'> 11.15KB </span>","children":null,"spread":false},{"title":"t_GR.v <span style='color:#111;'> 1.23KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]