一个简单双核CPU的verilog实现(加中断、异常处理,已通过实验箱验证)

上传者: liuxunyun | 上传时间: 2019-12-21 20:10:43 | 文件大小: 30KB | 文件类型: rar
一个简单双核CPU的verilog实现(加中断、异常处理已通过实验箱验证)可以实现双核交替访存,提高访问存储器效率,同时可以通过内存数据区实现双核数据的共享。

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评论信息

  • Rbjdllg :
    一点说明不给看的太费力了!
    2014-09-11
  • alpczy :
    功能有点强大了,初学者不适合
    2013-05-09
  • liu_xin243 :
    只是程序看不懂,希望有说明啊!!!
    2012-06-30
  • ylyshhz124 :
    没有结构图和指令集说明 不太方便
    2012-01-20

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