RISC_V 多周期CPU设计.zip

上传者: yuanfuli | 上传时间: 2019-12-25 11:52:33 | 文件大小: 60KB | 文件类型: zip
RISC_V 多周期CPU设计,里面包含基于最新提出的RISC_V指令集设计的多周期CPU,使用Verilog语言,代码注释详细,提供官方给出的测试样例,RV32I 基本整数指令四十多条指令都有实现,波形仿真通过。

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评论信息

  • qq_41512613 :
    Error (10839): Verilog HDL error at IM.v(76): declaring multiple packed array dimensions is a System
    2021-05-08
  • qq_41512613 :
    Error (10839): Verilog HDL error at IM.v(76): declaring multiple packed array dimensions is a System
    2021-05-08

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