基于Tomasulo算法的32位RISC带Cache的流水线CPU设计

上传者: xumo0611 | 上传时间: 2019-12-21 22:06:27 | 文件大小: 3.43MB | 文件类型: rar
清华大学电子系微机原理课程设计题目。4人合作完成。 包含CPU的VHDL、Verilog源代码、仿真文件、波形结果、系统框图、实验报告、以及一个简易汇编器的源代码和可执行文件。 Quartus仿真实现了32位RISC微处理器,支持数据处理(包括乘除法),数据传送,子程序调用,中断及跳转。时序仿真主频可达70MHz。 采用Tomasulo算法处理指令流水中的数据相关,并提出了一种对Tomasulo就够的改进。设计了Cache结构提高访存效率。

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[{"title":"( 53 个子文件 3.43MB ) 基于Tomasulo算法的32位RISC带Cache的流水线CPU设计","children":[{"title":"报告","children":[{"title":"微机原理课程设计报告.pdf <span style='color:#111;'> 3.13MB </span>","children":null,"spread":false}],"spread":true},{"title":"仿真波形","children":[{"title":"仿真波形二.sim.cvwf <span style='color:#111;'> 11.83KB </span>","children":null,"spread":false},{"title":"仿真波形一.sim.cvwf <span style='color:#111;'> 15.91KB </span>","children":null,"spread":false},{"title":"仿真波形三.sim.cvwf <span style='color:#111;'> 10.97KB </span>","children":null,"spread":false}],"spread":true},{"title":"汇编器及源程序","children":[{"title":"In.asm <span style='color:#111;'> 580B </span>","children":null,"spread":false},{"title":"Assembler.cpp <span style='color:#111;'> 23.00KB </span>","children":null,"spread":false},{"title":"Assembler.exe <span style='color:#111;'> 74.00KB </span>","children":null,"spread":false}],"spread":true},{"title":"图片","children":[{"title":"CACHE.jpg <span style='color:#111;'> 675.59KB </span>","children":null,"spread":false},{"title":"寄存器堆.png <span style='color:#111;'> 46.70KB </span>","children":null,"spread":false},{"title":"MMU.jpg <span style='color:#111;'> 496.25KB </span>","children":null,"spread":false},{"title":"STATION.jpg <span style='color:#111;'> 759.05KB </span>","children":null,"spread":false}],"spread":true},{"title":"CPU源代码","children":[{"title":"CPU","children":[{"title":"CPU.vwf <span style='color:#111;'> 238.90KB </span>","children":null,"spread":false},{"title":"mux_8.vhd <span style='color:#111;'> 585B </span>","children":null,"spread":false},{"title":"clk_delay.v <span style='color:#111;'> 417B </span>","children":null,"spread":false},{"title":"logic32.v <span style='color:#111;'> 4.89KB </span>","children":null,"spread":false},{"title":"MMU.V <span style='color:#111;'> 8.25KB </span>","children":null,"spread":false},{"title":"mux_32.vhd <span style='color:#111;'> 1.19KB </span>","children":null,"spread":false},{"title":"CPU.vhd <span style='color:#111;'> 27.96KB </span>","children":null,"spread":false},{"title":"STORE_STU.V <span style='color:#111;'> 15.08KB </span>","children":null,"spread":false},{"title":"PC.vhd <span style='color:#111;'> 651B </span>","children":null,"spread":false},{"title":"ALU_ADDSUB_level.v <span style='color:#111;'> 4.61KB </span>","children":null,"spread":false},{"title":"ALU_ST_ADDSUB.V <span style='color:#111;'> 9.03KB </span>","children":null,"spread":false},{"title":"and_7.vhd <span style='color:#111;'> 344B </span>","children":null,"spread":false},{"title":"decoder_32.vhd <span style='color:#111;'> 2.41KB </span>","children":null,"spread":false},{"title":"CACHE.V <span style='color:#111;'> 8.14KB </span>","children":null,"spread":false},{"title":"register_file.vhd <span style='color:#111;'> 6.31KB </span>","children":null,"spread":false},{"title":"ALU_ST_MUL.v <span style='color:#111;'> 8.27KB </span>","children":null,"spread":false},{"title":"FLAG_reg.vhd <span style='color:#111;'> 1.52KB </span>","children":null,"spread":false},{"title":"Shifter.v <span style='color:#111;'> 255B </span>","children":null,"spread":false},{"title":"MEM.v <span style='color:#111;'> 4.41KB </span>","children":null,"spread":false},{"title":"Controller.vhd <span style='color:#111;'> 4.33KB </span>","children":null,"spread":false},{"title":"ALU_SHIFT_level.v <span style='color:#111;'> 4.95KB </span>","children":null,"spread":false},{"title":"div.v <span style='color:#111;'> 57.38KB </span>","children":null,"spread":false},{"title":"ALU_DIV_level.v <span style='color:#111;'> 4.61KB </span>","children":null,"spread":false},{"title":"Instruction_processing_component.vhd <span style='color:#111;'> 6.82KB </span>","children":null,"spread":false},{"title":"ALU_ST_SHIFT.v <span style='color:#111;'> 8.76KB </span>","children":null,"spread":false},{"title":"LRU.V <span style='color:#111;'> 692B </span>","children":null,"spread":false},{"title":"MEM_INS.v <span style='color:#111;'> 217B </span>","children":null,"spread":false},{"title":"ADD_SUB.v <span style='color:#111;'> 4.72KB </span>","children":null,"spread":false},{"title":"RAM.DATA <span style='color:#111;'> 2.13KB </span>","children":null,"spread":false},{"title":"ALU_ST_DIV.v <span style='color:#111;'> 7.95KB </span>","children":null,"spread":false},{"title":"add_sub32.v <span style='color:#111;'> 3.24KB </span>","children":null,"spread":false},{"title":"CACHE_LINE.V <span style='color:#111;'> 2.95KB </span>","children":null,"spread":false},{"title":"mux_4.vhd <span style='color:#111;'> 449B </span>","children":null,"spread":false},{"title":"ALU_LOGIC_level.v <span style='color:#111;'> 4.83KB </span>","children":null,"spread":false},{"title":"shift.v <span style='color:#111;'> 1.47KB </span>","children":null,"spread":false},{"title":"yy.mif <span style='color:#111;'> 1.40KB </span>","children":null,"spread":false},{"title":"our_register_n.vhd <span style='color:#111;'> 936B </span>","children":null,"spread":false},{"title":"mult.v <span style='color:#111;'> 17.08KB </span>","children":null,"spread":false},{"title":"LD_STU.v <span style='color:#111;'> 12.18KB </span>","children":null,"spread":false},{"title":"ALU_ST_LOGIC.V <span style='color:#111;'> 8.40KB </span>","children":null,"spread":false},{"title":"ALU_MUL_level.v <span style='color:#111;'> 4.34KB </span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"ReadMe.txt <span style='color:#111;'> 328B </span>","children":null,"spread":false}],"spread":true}]

评论信息

  • baidu_17176047 :
    很详细,具有参考性。
    2015-11-06
  • baidu_17176047 :
    很详细,具有参考性。
    2015-11-06
  • twq1108 :
    清华大学的课程设计,目前准备做与cache实现有关的工作,该项目中包含了多周期流水线、cache、mmu等,比较全面,很有参考价值
    2014-10-27
  • twq1108 :
    清华大学的课程设计,目前准备做与cache实现有关的工作,该项目中包含了多周期流水线、cache、mmu等,比较全面,很有参考价值
    2014-10-27
  • kurumi_r :
    很不错,值得参考
    2013-10-24
  • KURUMI_R :
    很不错,值得参考
    2013-10-24
  • lxyera :
    文档很详细,想写个流水的IP核,参考了一下流水线的实现
    2013-08-22
  • lxyera :
    文档很详细,想写个流水的IP核,参考了一下流水线的实现
    2013-08-22
  • peanutyk :
    好东西。如果全是verilog的就更好了
    2013-06-22
  • peanutyk :
    好东西。如果全是verilog的就更好了
    2013-06-22

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