完整详尽官方DDR SDRAM CONTROLLER代码（非IP核）及使用文档

[{"title":"（ 62 个子文件 782KB ） 完整详尽官方DDR SDRAM CONTROLLER代码（非IP核）及使用文档","children":[{"title":"DDR设计参考说明及代码","children":[{"title":"simulation","children":[{"title":"work","children":[{"title":"mt46v4m16","children":[{"title":"_primary.vhd <span style='color:#111;'> 1.15KB </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 24.52KB </span>","children":null,"spread":false},{"title":"verilog.psm <span style='color:#111;'> 226.59KB </span>","children":null,"spread":false}],"spread":true},{"title":"ddr_data_path","children":[{"title":"_primary.vhd <span style='color:#111;'> 817B </span>","children":null,"spread":false},{"title":"_primary.dat <span style='color:#111;'> 3.14KB </span>","children":null,"spread":false},{"title":"verilog.psm <span style='color:#111;'> 23.52KB </span>","children":null,"spread":false}],"spread":true},{"title":"ddr_control_interface","children":[{"title":"_primary.vhd <span style='color:#111;'> 1.09KB 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