FPGA实现PCIe接口测试程序

[{"title":"（ 59 个子文件 3.9MB ） FPGA实现PCIe接口测试程序","children":[{"title":"ml605_pcie_x8_gen1","children":[{"title":"v6_pcie_v1_7_xmdf.tcl <span style='color:#111;'> 5.22KB </span>","children":null,"spread":false},{"title":"ml605_pcie_x8_gen1.cgp <span style='color:#111;'> 523B </span>","children":null,"spread":false},{"title":"ml605_pcie_x8_gen1.cgc <span style='color:#111;'> 82.74KB </span>","children":null,"spread":false},{"title":"ready_for_download","children":[{"title":"ml605_pcie_x8_gen1.mcs <span style='color:#111;'> 24.22MB </span>","children":null,"spread":false},{"title":"ml605_pcie_x8_gen1.prm <span style='color:#111;'> 765B </span>","children":null,"spread":false},{"title":"make_plat_mcs.bat <span style='color:#111;'> 130B </span>","children":null,"spread":false},{"title":"ml605_program_platflash.cmd <span style='color:#111;'> 253B </span>","children":null,"spread":false},{"title":"ml605_pcie_x8_gen1.cfi <span style='color:#111;'> 487B </span>","children":null,"spread":false}],"spread":true},{"title":"v6_pcie_v1_7.xise <span style='color:#111;'> 42.97KB </span>","children":null,"spread":false},{"title":"v6_pcie_v1_7_flist.txt <span style='color:#111;'> 2.82KB </span>","children":null,"spread":false},{"title":"v6_pcie_v1_7.xco <span style='color:#111;'> 5.90KB </span>","children":null,"spread":false},{"title":"v6_pcie_v1_7.veo <span style='color:#111;'> 7.58KB </span>","children":null,"spread":false},{"title":"v6_pcie_v1_7.gise <span style='color:#111;'> 1.15KB </span>","children":null,"spread":false},{"title":"v6_pcie_v1_7","children":[{"title":"example_design","children":[{"title":"pci_exp_8_lane_64b_ep.v <span style='color:#111;'> 12.68KB </span>","children":null,"spread":false},{"title":"PIO_64.v <span style='color:#111;'> 2.68KB </span>","children":null,"spread":false},{"title":"xilinx_pcie_2_0_ep_v6.v <span style='color:#111;'> 18.75KB </span>","children":null,"spread":false},{"title":"EP_MEM.v <span style='color:#111;'> 66.42KB </span>","children":null,"spread":false},{"title":"PIO_EP.v <span style='color:#111;'> 10.54KB </span>","children":null,"spread":false},{"title":"PIO_64_TX_ENGINE.v <span style='color:#111;'> 9.60KB </span>","children":null,"spread":false},{"title":"pcie_app_v6.v <span style='color:#111;'> 11.71KB </span>","children":null,"spread":false},{"title":"PIO_EP_MEM_ACCESS.v <span style='color:#111;'> 12.52KB </span>","children":null,"spread":false},{"title":"PIO_64_RX_ENGINE.v <span style='color:#111;'> 19.28KB </span>","children":null,"spread":false},{"title":"xilinx_pcie_2_0_ep_v6_08_lane_gen1_xc6vlx240t-ff1156-1_ML605.ucf <span style='color:#111;'> 7.19KB </span>","children":null,"spread":false},{"title":"PIO.v <span style='color:#111;'> 7.86KB </span>","children":null,"spread":false},{"title":"PIO_TO_CTRL.v <span style='color:#111;'> 3.98KB </span>","children":null,"spread":false}],"spread":false},{"title":"v6_pcie_readme.txt <span style='color:#111;'> 8.94KB </span>","children":null,"spread":false},{"title":"implement","children":[{"title":"xilinx_pcie_2_0_ep_v6.ngc_xst.xrpt <span style='color:#111;'> 13.98KB </span>","children":null,"spread":false},{"title":"xilinx_pcie_2_0_ep_v6.ngr <span style='color:#111;'> 2.09MB </span>","children":null,"spread":false},{"title":"xilinx_pcie_2_0_ep_v6.xcf <span style='color:#111;'> 350B </span>","children":null,"spread":false},{"title":"implement.log <span style='color:#111;'> 208.63KB </span>","children":null,"spread":false},{"title":"xilinx_pcie_2_0_ep_v6.prj <span style='color:#111;'> 1.09KB </span>","children":null,"spread":false},{"title":"implement.sh <span style='color:#111;'> 1.26KB </span>","children":null,"spread":false},{"title":"implement.bat <span style='color:#111;'> 1.14KB </span>","children":null,"spread":false},{"title":"results","children":[{"title":"routed.bit <span style='color:#111;'> 8.80MB </span>","children":null,"spread":false},{"title":"routed.par <span style='color:#111;'> 15.16KB </span>","children":null,"spread":false},{"title":"routed.ncd <span style='color:#111;'> 1.15MB </span>","children":null,"spread":false},{"title":"routed.pad <span style='color:#111;'> 42.26KB </span>","children":null,"spread":false},{"title":"mapped.mrp <span style='color:#111;'> 17.47KB </span>","children":null,"spread":false}],"spread":false},{"title":"xilinx_pcie_2_0_ep_v6.ngc <span style='color:#111;'> 1.39MB </span>","children":null,"spread":false},{"title":"xilinx_pcie_2_0_ep_v6.log <span style='color:#111;'> 173.85KB </span>","children":null,"spread":false},{"title":"xilinx_pcie_2_0_ep_v6.cmd <span style='color:#111;'> 302B </span>","children":null,"spread":false},{"title":"xst.srp <span style='color:#111;'> 173.85KB </span>","children":null,"spread":false}],"spread":false},{"title":"source","children":[{"title":"gtx_drp_chanalign_fix_3752_v6.v <span style='color:#111;'> 6.78KB </span>","children":null,"spread":false},{"title":"pcie_reset_delay_v6.v <span style='color:#111;'> 3.96KB </span>","children":null,"spread":false},{"title":"gtx_wrapper_v6.v <span style='color:#111;'> 25.89KB </span>","children":null,"spread":false},{"title":"gtx_rx_valid_filter_v6.v <span style='color:#111;'> 11.82KB </span>","children":null,"spread":false},{"title":"v6_pcie_v1_7.v <span style='color:#111;'> 52.00KB </span>","children":null,"spread":false},{"title":"pcie_brams_v6.v <span style='color:#111;'> 8.48KB </span>","children":null,"spread":false},{"title":"pcie_pipe_lane_v6.v <span style='color:#111;'> 12.49KB </span>","children":null,"spread":false},{"title":"pcie_pipe_misc_v6.v <span style='color:#111;'> 7.54KB </span>","children":null,"spread":false},{"title":"pcie_clocking_v6.v <span style='color:#111;'> 11.27KB </span>","children":null,"spread":false},{"title":"pcie_2_0_v6.v <span style='color:#111;'> 80.28KB </span>","children":null,"spread":false},{"title":"pcie_gtx_v6.v <span style='color:#111;'> 23.74KB </span>","children":null,"spread":false},{"title":"pcie_upconfig_fix_3451_v6.v <span style='color:#111;'> 7.20KB </span>","children":null,"spread":false},{"title":"pcie_bram_v6.v <span style='color:#111;'> 11.46KB </span>","children":null,"spread":false},{"title":"gtx_tx_sync_rate_v6.v <span style='color:#111;'> 14.25KB </span>","children":null,"spread":false},{"title":"pcie_pipe_v6.v <span style='color:#111;'> 35.51KB </span>","children":null,"spread":false},{"title":"pcie_bram_top_v6.v <span style='color:#111;'> 5.90KB </span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"readme.txt <span style='color:#111;'> 3.34KB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]