Xilinx Vivado User Guides 赛灵思Vivado软件使用手册合集

[{"title":"（ 21 个子文件 62.21MB ） Xilinx Vivado User Guides 赛灵思Vivado软件使用手册合集","children":[{"title":"Xilinx Vivado User Guides","children":[{"title":"20.Design Analysis and ClosureTechniques.pdf <span style='color:#111;'> 9.56MB </span>","children":null,"spread":false},{"title":"9.Model-Based DSP DesignUsing System Generator.pdf <span style='color:#111;'> 8.49MB </span>","children":null,"spread":false},{"title":"17.Hierarchical Design.pdf <span style='color:#111;'> 443.82KB </span>","children":null,"spread":false},{"title":"5.Using Tcl Scripting5..pdf <span style='color:#111;'> 2.80MB </span>","children":null,"spread":false},{"title":"3.Design Flows Overview.pdf <span style='color:#111;'> 2.17MB </span>","children":null,"spread":false},{"title":"15.Synthesis.pdf <span style='color:#111;'> 5.15MB </span>","children":null,"spread":false},{"title":"18.Partial Reconfiguration.pdf <span style='color:#111;'> 2.61MB </span>","children":null,"spread":false},{"title":"4.Using the Vivado IDE.pdf <span style='color:#111;'> 4.23MB </span>","children":null,"spread":false},{"title":"6.Designing with IP.pdf <span style='color:#111;'> 2.59MB </span>","children":null,"spread":false},{"title":"7.Creating and PackagingCustom IP.pdf <span style='color:#111;'> 2.27MB </span>","children":null,"spread":false},{"title":"21.Programming and Debugging.pdf <span style='color:#111;'> 8.21MB </span>","children":null,"spread":false},{"title":"8.Embedded ProcessorHardware Design.pdf <span style='color:#111;'> 6.37MB </span>","children":null,"spread":false},{"title":"14.Using Constraints.pdf <span style='color:#111;'> 3.60MB </span>","children":null,"spread":false},{"title":"2.Design Flows Overview.pdf <span style='color:#111;'> 2.17MB </span>","children":null,"spread":false},{"title":"12.Logic Simulation.pdf <span style='color:#111;'> 4.10MB </span>","children":null,"spread":false},{"title":"1.Getting Start.pdf <span style='color:#111;'> 364.58KB </span>","children":null,"spread":false},{"title":"10.High-Level Synthesis.pdf <span style='color:#111;'> 10.54MB </span>","children":null,"spread":false},{"title":"11.IO and Clock Planning.pdf <span style='color:#111;'> 2.77MB </span>","children":null,"spread":false},{"title":"13.Xilinx Power EstimatorUser Guide.pdf <span style='color:#111;'> 2.52MB </span>","children":null,"spread":false},{"title":"16.Implementation.pdf <span style='color:#111;'> 3.56MB </span>","children":null,"spread":false},{"title":"19.Power Analysis andOptimization.pdf <span style='color:#111;'> 2.61MB </span>","children":null,"spread":false}],"spread":false}],"spread":true}]