首页 数字系统设计(FPGA)：多功能数字钟工程文件

数字系统设计(FPGA)：多功能数字钟工程文件

上传者： 51204094 | 上传时间： 2023-03-12 01:40:09 | 文件大小： 2.24MB | 文件类型： ZIP
一、要求：实现多功能数字钟，具备下列功能： 1、数字钟：能计时，实现小时、分钟、秒的显示； 2、数字跑表：精度至0.01秒 比如显示12.97秒； 3、闹钟: 可以设定闹钟，用试验箱上的蜂鸣器作为闹铃； 4、调时：可以对时间进行设定； 5、日期设定：能设定日期并显示当前日期； 6、除调时状态，其他状态均不应影响系统计时。 二、设计方案与设计思路： 整体程序通过例化10个模块后整合形成多功能数字时钟功能，各模块名称以及各模块的作用分别为： 1、总控制模块：用于控制调整时分秒、年月日以及闹钟的模式选择，以及控制三个add按键调整的对象。 2、分频器模块：用于分频得到1Hz计时时钟。 3、时分秒调整模块：处于计时器时分秒调整设置状态时，对应控制模块的三个add按键可以实现对计时器的时分秒数值的设置，并且有按键可以实现对时分秒模块进行设置数值的载入。 4、时分秒变量处理（计时）模块：用于计时，根据分频后的时钟每隔一秒使秒变量加一，满六十向分变量进一，以此类推实现分钟以及小时的进位。 5、年月日调整模块：处于日期年月日调整设置状态时，对应控制模块的三个add

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