采用verilogHDL编写的数字跑表

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23.59KB </span>","children":null,"spread":false},{"title":"paobiao.syr <span style='color:#111;'> 15.87KB </span>","children":null,"spread":false},{"title":"paobiao.prj <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"paobiao.bgn <span style='color:#111;'> 5.01KB </span>","children":null,"spread":false},{"title":"paobiao_summary.html <span style='color:#111;'> 4.74KB </span>","children":null,"spread":false},{"title":"paobiao.ncd <span style='color:#111;'> 14.89KB </span>","children":null,"spread":false},{"title":"paobiao.ngm <span style='color:#111;'> 38.80KB </span>","children":null,"spread":false},{"title":"paobiao.routed_ncd_tracker <span style='color:#111;'> 0B </span>","children":null,"spread":false},{"title":"paobiao.ngd <span style='color:#111;'> 19.81KB </span>","children":null,"spread":false},{"title":"paobiao.pcf <span style='color:#111;'> 318B </span>","children":null,"spread":false},{"title":"paobiao_tb.tfw <span style='color:#111;'> 4.63KB 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