verliog设计实现实时时钟DS1302的驱动工程源码，quartus11.0G工程文件，FPGA为CYCLONE4E ep4ce15f17c8.rar

[{"title":"（ 99 个子文件 3.52MB ） verliog设计实现实时时钟DS1302的驱动工程源码，quartus11.0G工程文件，FPGA为CYCLONE4E ep4ce15f17c8.rar","children":[{"title":"ds1302","children":[{"title":"ds1302.pin <span style='color:#111;'> 31.74KB </span>","children":null,"spread":false},{"title":"tcl","children":[{"title":"13_osh.tcl <span style='color:#111;'> 631B </span>","children":null,"spread":false}],"spread":true},{"title":"ds1302.done <span style='color:#111;'> 26B </span>","children":null,"spread":false},{"title":"ds1302.fit.rpt <span style='color:#111;'> 144.64KB </span>","children":null,"spread":false},{"title":"source","children":[{"title":"exp13_demo.v <span style='color:#111;'> 1.68KB </span>","children":null,"spread":false},{"title":"ds1302_module.v <span style='color:#111;'> 1.56KB </span>","children":null,"spread":false},{"title":"function_module.v.bak <span style='color:#111;'> 3.32KB </span>","children":null,"spread":false},{"title":"cmd_control_module.v <span style='color:#111;'> 2.77KB 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