Altera_arriaVST_5astfd5kf40es_soc开发板cadence orcad硬件原理图+PCB文件.zip

上传者: GJZGRB | 上传时间: 2021-01-30 20:08:01 | 文件大小: 12.64MB | 文件类型: ZIP
Altera_arriaVST_5astfd5kf40es_soc开发板cadence orcad硬件原理图+PCB文件,Cadence Allegro设计文件,可作为你产品设计的参考。

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[{"title":"( 19 个子文件 12.64MB ) Altera_arriaVST_5astfd5kf40es_soc开发板cadence orcad硬件原理图+PCB文件.zip","children":[{"title":"arriaVST_5astfd5kf40es_soc","children":[{"title":"bom","children":[{"title":"arriaV_SoC_revc_ bom__customer.xls <span style='color:#111;'> 72.50KB </span>","children":null,"spread":false}],"spread":true},{"title":"schematic","children":[{"title":"A5_SOC_DEVKIT_C.DSN <span style='color:#111;'> 10.16MB </span>","children":null,"spread":false},{"title":"revc_changes.txt <span style='color:#111;'> 158B </span>","children":null,"spread":false},{"title":"A5_SOC_DEVKIT_C.pdf <span style='color:#111;'> 1.40MB </span>","children":null,"spread":false}],"spread":true},{"title":"assembly","children":[{"title":"130-0320807-C1_assy.pdf <span style='color:#111;'> 284.51KB </span>","children":null,"spread":false}],"spread":true},{"title":"layout","children":[{"title":"manufacturing","children":[{"title":"140-0320807-C1_fab.pdf <span style='color:#111;'> 132.83KB </span>","children":null,"spread":false}],"spread":true},{"title":"140-0320807-C1.brd <span style='color:#111;'> 30.42MB </span>","children":null,"spread":false}],"spread":true},{"title":"signal_integrity","children":[{"title":"ALTERA 18 layers_ Arria V SoC.pdf <span style='color:#111;'> 79.20KB </span>","children":null,"spread":false},{"title":"board_trace_delays","children":[{"title":"a5soc_timing_by_length.pl <span style='color:#111;'> 6.13KB </span>","children":null,"spread":false},{"title":"av_soc_ddr3_lengths.csv <span style='color:#111;'> 98.93KB </span>","children":null,"spread":false},{"title":"AV_SoC_DDR3B.xlsx <span style='color:#111;'> 20.88KB </span>","children":null,"spread":false},{"title":"AV_SoC_DDR3_HPS.xlsx <span style='color:#111;'> 21.03KB </span>","children":null,"spread":false},{"title":"AV_SoC_DDR3A_timing.csv <span style='color:#111;'> 627B </span>","children":null,"spread":false},{"title":"extract_timing_model.pl <span style='color:#111;'> 11.56KB </span>","children":null,"spread":false},{"title":"elp_rep.rpt <span style='color:#111;'> 75.25KB </span>","children":null,"spread":false},{"title":"AV_SoC_DDR3C_timing.csv <span style='color:#111;'> 465B </span>","children":null,"spread":false},{"title":"AV_SoC_DDR3B_timing.csv <span style='color:#111;'> 625B </span>","children":null,"spread":false},{"title":"AV_SoC_DDR3_HPS_timing.csv <span style='color:#111;'> 706B </span>","children":null,"spread":false},{"title":"AV_SoC_DDR3A.xlsx <span style='color:#111;'> 20.85KB </span>","children":null,"spread":false}],"spread":false}],"spread":true},{"title":"power","children":null,"spread":false}],"spread":true}],"spread":true}]

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