业界通用验证方法学。包内包括userguide, reference, source code, examples.

转载《A Practical Guide to Adopting the Universal Verification Methodology》 的中文版，不是《UVM实战》也不是《The UVM Primer》，翻译者不详

There are a multitude of books out there to help you hone your Verification skills, as almost every Digital IC professional will tell you. The available books run the gamut of quality and ease of use. The major strength of this book is a place where many of those books fall down – they are not what they claim to be. Vanessa’s book is a great example of exactly what it claims to be – a guide for the “beginner”. “Beginner” is used loosely in this context because the book does not shy away from advanced concepts (the Factory, register package prediction, etc.)

这个文档是超级有用的噻。列出部分的目录 Overview 1.1 Scope 1.2 Purpose 2. Normative References 3. Definitions, Acronyms, and Abbreviations 3.1 Definitions 3.2 Acronyms and Abbreviations 4. Classes and Utilities 5. Base Classes 5.1 uvm_void 5.2 uvm_object 5.3 uvm_transaction 5.4 uvm_root 5.5 uvm_port_base 6. Reporting Classes 6.1 uvm_report_object 6.2 uvm_report_handler 6.3 uvm_report_server 6.4 uvm_report_catcher 7. Factory Classes 7.1 uvm_*_registry 7.2 uvm_factory 8. Phasing Classes 8.1 uvm_phase 8.2 uvm_domain 8.3 uvm_bottomup_phase 8.4 uvm_task_phase 8.5 uvm_topdown_phase 8.6 UVM Common Phases UVM 1.1 Class Reference Front-4 8.7 UVM Run-Time Phases 8.8 User-Defined Phases 9. Configuration and Resource Classes 9.1 uvm_resource 9.2 uvm_resource_db 9.3 uvm_config_db 10. Synchronization Classes . 10.1 uvm_event 10.2 uvm_event_callback 10.3 uvm_barrier 10.4 uvm_objection 10.5 uvm_heartbeat

包含英文技术手册，及国内实际开发者编写的教程；另外，也会上传system verilog的中文教程，便于理解UVM的开发。通用验证方法学（Universal Verification Methodology, UVM）是一个以SystemVerilog类库为主体的验证平台开发框架，验证工程师可以利用其可重用组件构建具有标准化层次结构和接口的功能验证环境。

uvm_ref_flow_2013.05，cadence最新的UVMdemo